bitkeeper revision 1.1159.34.1 (4120f807tIRvdXAnGlpEWbbgD_eByQ)
authorkaf24@scramble.cl.cam.ac.uk <kaf24@scramble.cl.cam.ac.uk>
Mon, 16 Aug 2004 18:08:07 +0000 (18:08 +0000)
committerkaf24@scramble.cl.cam.ac.uk <kaf24@scramble.cl.cam.ac.uk>
Mon, 16 Aug 2004 18:08:07 +0000 (18:08 +0000)
Speed up the context-switch path on 2.6.

.rootkeys
linux-2.6.7-xen-sparse/arch/xen/i386/kernel/process.c
linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/mmu_context.h [new file with mode: 0644]
linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/processor.h

index a98b08862998cb7421fbc4c6c53d033ca83e5cea..f03b2039ecf78ca77aad4524980e30c37bc3d723 100644 (file)
--- a/.rootkeys
+++ b/.rootkeys
 41062ab7HMSSuaUv3_Z4agLpjSO88A linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/mach-xen/pci-functions.h
 40f5623aDMCsWOFO0jktZ4e8sjwvEg linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_post.h
 40f5623arsFXkGdPvIqvFi3yFXGR0Q linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_pre.h
+4120f807GCO0uqsLqdZj9csxR1Wthw linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/mmu_context.h
 40f5623aFTyFTR-vdiA-KaGxk5JOKQ linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/msr.h
 40f5623adgjZq9nAgCt0IXdWl7udSA linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/page.h
 40f5623a54NuG-7qHihGYmw4wWQnMA linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/param.h
index da60123dfd0e53de87c81e5bd2ca0f9646c6ec56..f519ba1c5e32775548bc7e53d138b29e6651a049 100644 (file)
@@ -502,10 +502,10 @@ struct task_struct fastcall * __switch_to(struct task_struct *prev_p, struct tas
                                 *next = &next_p->thread;
        int cpu = smp_processor_id();
        struct tss_struct *tss = init_tss + cpu;
-       unsigned long flags;
        dom0_op_t op;
 
-       local_irq_save(flags);
+        /* NB. No need to disable interrupts as already done in sched.c */
+        /* __cli(); */
 
        /*
         * Save away %fs and %gs. No need to save %es and %ds, as
@@ -569,8 +569,7 @@ struct task_struct fastcall * __switch_to(struct task_struct *prev_p, struct tas
 
        /* EXECUTE ALL TASK SWITCH XEN SYSCALLS AT THIS POINT. */
        execute_multicall_list();
-
-       local_irq_restore(flags);
+        /* __sti(); */
 
        /*
         * Restore %fs and %gs if needed.
diff --git a/linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/mmu_context.h b/linux-2.6.7-xen-sparse/include/asm-xen/asm-i386/mmu_context.h
new file mode 100644 (file)
index 0000000..cea0fd6
--- /dev/null
@@ -0,0 +1,75 @@
+#ifndef __I386_SCHED_H
+#define __I386_SCHED_H
+
+#include <linux/config.h>
+#include <asm/desc.h>
+#include <asm/atomic.h>
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+
+/*
+ * Used for LDT copy/destruction.
+ */
+int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
+void destroy_context(struct mm_struct *mm);
+
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+#ifdef CONFIG_SMP
+       unsigned cpu = smp_processor_id();
+       if (cpu_tlbstate[cpu].state == TLBSTATE_OK)
+               cpu_tlbstate[cpu].state = TLBSTATE_LAZY;        
+#endif
+}
+
+static inline void switch_mm(struct mm_struct *prev,
+                            struct mm_struct *next,
+                            struct task_struct *tsk)
+{
+       int cpu = smp_processor_id();
+
+       if (likely(prev != next)) {
+               /* stop flush ipis for the previous mm */
+               cpu_clear(cpu, prev->cpu_vm_mask);
+#ifdef CONFIG_SMP
+               cpu_tlbstate[cpu].state = TLBSTATE_OK;
+               cpu_tlbstate[cpu].active_mm = next;
+#endif
+               cpu_set(cpu, next->cpu_vm_mask);
+
+               /* Re-load page tables */
+               load_cr3_noflush(next->pgd);
+
+               /*
+                * load the LDT, if the LDT is different:
+                */
+               if (unlikely(prev->context.ldt != next->context.ldt))
+                       load_LDT_nolock(&next->context, cpu);
+       }
+#ifdef CONFIG_SMP
+       else {
+               cpu_tlbstate[cpu].state = TLBSTATE_OK;
+               BUG_ON(cpu_tlbstate[cpu].active_mm != next);
+
+               if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
+                       /* We were in lazy tlb mode and leave_mm disabled 
+                        * tlb flush IPI delivery. We must reload %cr3.
+                        */
+                       load_cr3_noflush(next->pgd);
+                       load_LDT_nolock(&next->context, cpu);
+               }
+       }
+#endif
+}
+
+#define deactivate_mm(tsk, mm) \
+       asm("movl %0,%%fs ; movl %0,%%gs": :"r" (0))
+
+#define activate_mm(prev, next) \
+do { \
+       switch_mm((prev),(next),NULL); \
+       flush_page_update_queue();                      \
+} while ( 0 )
+
+#endif
index a57533dd8a19093fa71d762db226918996417699..b4eafd19f76f22e36040e1ce6393b5eb0179f0b1 100644 (file)
@@ -186,6 +186,11 @@ static inline unsigned int cpuid_edx(unsigned int op)
        cur_pgd = pgdir;        /* XXXsmp */            \
 } while (/* CONSTCOND */0)
 
+#define load_cr3_noflush(pgdir) do {                   \
+       queue_pt_switch(__pa(pgdir));                   \
+       cur_pgd = pgdir;        /* XXXsmp */            \
+} while (/* CONSTCOND */0)
+
 
 /*
  * Intel CPU features in CR4